1. Field of the Invention
The present invention relates generally to a microcomputer and more specifically to a data bus arrangement which improves the speed with which data can be moved within the system.
2. Description of the Prior Art
Currently-used microcomputers inevitably include on a single silicon chip, a central processing unit CPU, a read only memory ROM, a random access memory RAM, an input output interface I/O, and a timer or clock circuit.
The CPU of such devices includes a register, an arithmetical unit (ALU), and an internal data bus which is used to transfer data between the two. These devices further include an external data bus which is used in conjunction with the internal bus to move data to peripheral circuits.
FIG. 1 shows an example of how the currently-used prior art devices have managed the movement of data.
Data from the internal register of the CPU is inputted to the ALU and subsequently processed. The result is latched in a temporary register. This data is then transferred to the internal data bus, latched in an output data latch and outputted therefrom to the external data bus. The data appearing on the output terminal of the chip is transferred into a memory located eternally of the chip on which the CPU and ALU are formed.
FIG. 2 depicts the number of bus cycles required to achieve the above mentioned data transfer. In the first half of the first bus cycle (nth bus cycle) data from the internal register is inputted to the ALU. In the latter half of the same cycle, data is processed and, at the same time, the internal bus is precharged. During the first half of the next cycle (viz., the n+1 cycle) the temporary charge is stored by temporarily latching the same. During the second half of this cycle, data is outputted to the external bus, and in the first half of the n+2 cycle, the data is written into an external memory.
Thus, as will be clear, there is a full bus cycle between the one in which data is inputted to the ALU and the one in which data from the CPU is actually written into memory. In this case, the result from the ALU is determined during the first half of the n+1 cycle but even though the processing is complete a total of three full bus cycles are required to transfer the data.
In addition to the above, the currently used devices have included circuit arrangements such as shown in FIG. 3. In this figure, numeral 1a denotes a ROM, and numerals 2a, 2b, 2c and 2d denote internal function registers which act as a program counter, a common use register, a stack pointer, an accumulator, and a program status word, respectively. These internal function registers 2a-2d are connected by way of an internal data bus 3, a data buffer 4, and an external bus 5 to a peripheral function register 6.
The data contained in these internal function registers 2a-2d is transferred to the peripheral function register 6 through the above mentioned internal bus 3, the data buffer 4 and the external bus 5, while in the reverse instance the data in the peripheral function register is supplied via the same path.
However, with this type of arrangement, the rate at which the bus can actually move data is insufficiently high to meet high speed processing requirements and hampers the attainment of currently required data speed handling and management targets.